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MICRONAS
MAS 3504D G.729 Annex A Voice Codec
Edition Nov. 7, 2001 6251-522-1DS
MICRONAS
MAS 3504D
Contents Page 4 4 5 5 5 6 6 6 6 6 6 6 6 6 7 7 8 8 8 8 9 9 10 10 10 11 11 12 12 12 13 13 14 14 14 14 14 15 15 15 16 16 16 16 17 Section 1. 1.1. 1.2. 1.2.1. 1.2.2. 2. 2.1. 2.2. 2.2.1. 2.2.2. 2.3. 2.4. 2.5. 2.5.1. 2.5.2. 2.5.3. 2.5.4. 2.6. 2.6.1. 2.6.2. 2.6.3. 2.6.3.1. 2.6.3.2. 2.6.4. 2.6.5. 2.6.5.1. 2.6.5.2. 3. 3.1. 3.1.1. 3.2. 3.2.1. 3.3. 3.3.1. 3.3.2. 3.3.3. 3.3.4. 3.3.5. 3.3.6. 3.3.7. 3.4. 3.5. 3.5.1. 3.5.2. 3.5.2.1. Title Introduction Features Application Overview Decoder Mode Encoder Mode Functional Description of the MAS 3504D DSP Core Firmware (Internal Program ROM) G.729 Encoder G.729 Decoder Program Download Feature Clock Management Power Supply Concept Internal Voltage Monitor DC/DC Converter Stand-by Functions Start-up Sequence Interfaces Parallel Input Output Interface (PIO) Parallel Data Output Parallel Data Input DMA Handshake Protocol End of DMA Transfer Audio Input Interface (SDI) Audio Output Interface (SDO) Example 1:16 Bits/Sample (I2S Compatible Data Format) Example 2:32 Bit/Sample (Inverted SOI) Control Interfaces I2C Bus Interface Device address and Subaddresses Command Structure Conventions for the Command Description Detailed MAS 3504D Command Syntax Run Write Register Write D0 Memory Write D1 Memory Read Register Read D0 Memory Read D1 Memory Version Number Register Table DC/DC Converter (Reg. 8Ehex) User Control (Reg. FDhex) Data Transmission Format
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MAS 3504D
Contents, continued Page 17 17 18 18 18 18 18 18 18 22 22 23 25 25 25 25 25 25 25 26 26 26 26 26 27 28 28 29 30 31 32 33 34 36 40 Section 3.5.2.2. 3.5.2.3. 3.5.2.4. 3.5.3. 3.5.4. 3.5.4.1. 3.5.4.2. 3.5.4.3. 3.5.5. 4. 4.1. 4.2. 4.2.1. 4.2.1.1. 4.2.1.2. 4.2.1.3. 4.2.1.4. 4.2.1.4.1. 4.2.1.4.2. 4.2.1.5. 4.2.1.6. 4.2.1.7. 4.2.1.8. 4.2.2. 4.2.3. 4.2.4. 4.2.4.1. 4.2.4.2. 4.2.4.3. 4.2.4.3.1. 4.2.4.3.2. 4.2.4.3.3. 4.2.4.4. 4.2.4.5. 5. Title Encoder Operation Decoder Operation Pause and Mute Volume Control (Reg. FChex) Interface Control Wordlength Control (Reg. 74hex) Input Configuration (Reg. 61hex) Output Configuration (Reg. E1hex) Hardware Control (Reg. FAhex) Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins DC/DC Converter Pins Control Lines Parallel Interface Lines PIO Handshake Lines PIO Data Lines Voltage Supervision And Other Functions Serial Input Interface Serial Output Interface Miscellaneous Pin Configurations Internal Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics I2C Characteristics I2S Bus Characteristics - SDI I2S Characteristics - SDO DC/DC Converter Characteristics Typical Performance Characteristics Data Sheet History
License Notice Supply of this implementation of G.729A technology does not convey a license nor imply any right to use this implementation in any finished end-user or ready-to-use final product. An independant license for such use is required. For information on such license agreement please contact: Sipro Lab Telecom Inc. email: patriciam@sipro.com http://www.sipro.com Fax: +1 (514) 737-2327
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MAS 3504D
G.729 Annex A Voice Codec 1. Introduction The MAS 3504D is a single-chip codec for use in memory-based voice recording and playback applications. Due to embedded memories, the embedded DC/ DC up-converter, and the very low power consumption, the MAS 3504D is ideally suited for portable electronics. The MAS 3504D implements a voice encoder and decoder that is compliant to the ITU Standard G.729 Annex A. This standard works on 8 kHz, 16 bit, mono audio data that is compressed to 1 bit per audio sample. One second of compressed audio data uses 1000 bytes of memory. 1.1. Features - Single-chip G.729 decoder - G.729 Annex A encoder - ITU compliance tests passed - Parallel input and parallel output of coded bitstream data - Input audio data read from an I2S bus (in various formats) - Output audio data delivered via an I2S bus (in various formats) - Digital volume / mute - Low power dissipation (150 mW for encoder, 80 mW for decoder @ 3.3 V) - Supply voltage range: 1.0 V to 3.6 V due to built-in DC/DC converter (1-cell battery operation) - Adjustable power supply supervision - Power-off function - Additional functionality achievable via download software (ADPCM encoder/decoder)
CLKI
Clock Synthesizer
MAS 3504D
DC/DC Converter
/3/
decoded output /3/
Serial Out I2S
parallel I/O RISC DSP Core PIO /8+5/
voice audio data /3/
Serial In
I2C
serial control /2/
Fig. 1-1: MAS 3504D block diagram
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1.2. Application Overview The MAS 3504D can be applied in two major environments: as standalone decoder or as encoder/decoder combination. For decoding only mode, the DAC 3550A fits perfectly to the requirements of the MAS 3504D. It is a high-quality multi sample rate DAC (8 kHz.. 50 kHz) with internal crystal oscillator, which is only needed for generating the decoder Clock, and integrated stereo headphone amplifier plus two stereo inputs. A delayed response of the host to the request signal (max. 20 milliseconds) will be tolerated by the MAS 3504D as long as the input buffer does not run empty. A PC might use its DMA capabilities to transfer the data in the background to the MAS 3504D without interfering with its foreground processes. The source of the bit stream may be a memory (e.g. ROM, Flash) or PC peripherals, such as CD-ROM drive, a hard disk or a floppy disk drive.
1.2.2. Encoder Mode 1.2.1. Decoder Mode In a memory-based voice playback environment, the decoding is started with a command from a controller. Then the MAS 3504D continuously requests frames of G.729 data every 10 ms via the parallel (PIO) interface. For encoding a support routine must be downloaded to the MAS 3504D via I2C. After the encoder is started, it begins to encode the incoming audio data and writes the coded datastream to the parallel (PIO) interface. A delayed response of the host to the data available signal (max. 20 milliseconds) will be tolerated by the MAS 3504D as long as the output buffer does not overrun.
I2C Host (PC, Controller) demand signal demand clock G.729 bit stream CLKI MAS 3504D I2S
18.432 MHz DAC 3550A line out
ROM, CD-ROM, RAM, Flash Mem. ..
CLKOUT
Fig. 1-2: Block diagram of a MAS 3504D, decoding a stored bit stream in a decoding only application
I2C Host (PC, Controller) Handshake signals G.729 bit stream
data in data out MAS 3504D strobe clock I2S lines CLKI
AD/DA
line in Mic in line out
PLL
ROM, CD-ROM, RAM, Flash Mem. .. Fig. 1-3: Block diagram of a MAS 3504D in an encoding/decoding application
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MAS 3504D
2. Functional Description 2.1. DSP Core The hardware of the MAS 3504D consists of a high performance Digital Signal Processor and appropriate interfaces. The processor works with a memory word length of 20 bits and an extended range of 32 bits in its accumulators. The instruction set of the DSP is highly optimized for audio data compression and decompression. Thus, only very small areas of internal RAM and ROM are required. All data input and output actions are based on a `non cycle stealing' background DMA that does not cause any computational overhead. 2.3. Program Download Feature The overall function of the MAS 3504D can be altered by downloading up to 1 kWord program code into the internal RAM and by executing this code instead of the ROM code. During this time, G.729 processing is not possible. The code must be downloaded by the `write to memory' command (see Section 3.3. on page 14) into an area of internal RAM. A `run' command starts the operation. Micronas provides modules for encoding and decoding audio data with ADPCM. Detailed information about downloading is provided in combination with the MAS 3504D software development package from Micronas.
2.2. Firmware (Internal Program ROM) The firmware fully contains a G.729 voice decoder. With an additional support routine the IC is extended to a G.729 Annex A encoder. The G.729 standard compresses 8 kHz/16 bit mono voice data in frames of 80 samples to 10 bytes each, what results in a compressed bitstream of 1 bit/sample. The encoding according to Annex A has reduced complexity, but is fully compatible to the initial G.729 standard. Therefore the MAS 3504D can decode bitstreams that were encoded by other G.729 encoders and it can encode bitstreams that can be decoded with other G.729 decoders.
2.4. Clock Management The MAS 3504D should be driven by a single clock at a frequency of 18.432 MHz. The CLKI signal acts as a reference for the embedded clock synthesizer that generates the internal system clock.
2.5. Power Supply Concept 2.2.1. G.729 Encoder For encoding operation the MAS 3504D has to be prepared by downloading an additional routine to support the encoder. After starting the encoder, 80 audio samples are continuously read via the serial input interface. Each audio block of 80 samples is encoded to a G.729 data frame consisting of 10 bytes which is sent via the parallel interface. It is possible to monitor the input audio samples also directly via the serial output interface. The MAS 3504D offers an embedded controlled DC/ DC converter and voltage monitoring circuits for battery based power supply concepts. It works as an upconverter. The application circuit for the DC/DC converter is shown in Fig. 2-1.
2.5.1. Internal Voltage Monitor An internal voltage monitor compares the input voltage at the VSENS pin with an internal reference value that is adjustable via I2C bus. The PUP output pin becomes inactive when the voltage at the VSENS pin drops below the programmed value of the reference voltage. It is important that the WSEN must not be activated before the PUP is generated. The PUP signal thresholds are listed in Table 3-8 on page 19.
2.2.2. G.729 Decoder The MAS 3504D expects a sequence of valid G.729 frames (10 bytes each) as input. The compressed data is sent via the parallel interface. Each frame is decoded to 80 audio samples, modified by the volume/ mute control and sent out via the serial output interface.
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2.5.2. DC/DC Converter The DC/DC converter of the MAS 3504D is used to generate a fixed power supply voltage even if the chip is powered by battery cells in portable applications. The DC/DC converter is designed for the application of 1 or 2 batteries or NiCd cells. The DC/DC converter is switched on by activating the DCEN pin. Its output power is sufficient for other ICs as well. A 22 H inductor is required for the application. The important specification item is the inductor saturation current rating, which should be greater than 2.5 times the DC load current. The DC resistance of the inductor is important for efficiency. The primary criterion for selecting the output filter capacitor is low equivalent series resistance (ESR), as the product of the inductor current variation and the ESR determines the high-frequency amplitude seen on the output voltage. The Schottky diode should have a low voltage drop VD for a high overall efficiency of the DC/DC converter. The current rating of the diode should also be greater than 2.5 times the DC output current. The VSENS pin is always connected to the output voltage at the low ESR capacitor. 2.5.3. Stand-by Functions The digital part of the MAS 3504D and the DC/DC converter are turned on by setting WSEN. If only the DC/ DC converter should work, it can remain active bysetting DCEN alone to supply other parts of the application even if the audio decoding part of the MAS 3504D is not being used. The WSEN power-up pin of the digital part should be handled by the controller. Please pay attention to the fact, that the I2C interface is working only if the processor is powered up (WSEN = 1).
CLKI
VDD Start-up oscillator Start-up divider
64...94
x2
AVDD DCSO DCSG DC/DC converter
optional filter
22 H
+ -
COUT 330 F Low ESR
+
32...47
+32
DCEN voltage monitor PUP WSEN
16
Power-On Push Button
VIN 0.9 V
CIN 330 F
-
DCCF 8ehex 9 10
0...15
10 k
VSENSE VSS AVSS
47 k 10 nF 47 k
Controller
Fig. 2-1: DC/DC converter connections
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2.5.4. Start-up Sequence The DC/DC converter starts from a minimum input voltage of 0.9 V. There should be no output load during startup. In case WSEN is active, the MAS 3504D is in the DSP operation mode. The start-up script should be as follows: 1. Enable the DC/DC-converter with a high signal (VDD, AVDD) at pin DCEN. 2. Wait until PUP goes "high". 3. Wait one more millisecond to guarantee that the output voltage has settled (recommended). 4. Enable the MAS 3504D with a "high" signal at pin "WSEN". Please also refer to Figure 2-2. 2.6.2. Parallel Data Output 2.6. Interfaces The MAS 3504D uses an I2C control interface, a parallel I/O interface (PIO) for G.729- or ADPCM-data, a digital audio input interface (SDI) for audio data input and a digital audio output interface (SDO) for the decoded audio data (I2S or similar). The G.729 bit stream generated by an encoder is aligned in frames of 10 bytes. The parallel data required from the G.729 decoder must be sent in byteswapped order related to the standard specification. The G.729 encoder also sends the encoded bit stream byte-swapped to the PIO interface. In encoding mode, PIO lines PI12...PI19 are switched to the MAS 3504D data output which hence will be an 8-bit parallel output port with MSB first (at position PI19) for the G.729 bit stream data. The data is transferred in bursts of 10 bytes (1 frame) each 10 ms. If the transmission of headers is enabled, there is an additional 10 byte burst before each sequence of 50 frames. Handshaking for PIO output mode is accomplished through the RTW, PCS, and PI12..PI19 signal lines (see Fig. 2-3). The PR line has to be set to high level. RTW will go low as soon as a byte is available in the output buffer and will stay low until a byte has been read. Reading of a byte is performed with a PCS pulse. Data is latched out from the MAS 3504D on the falling edge of PCS and removed from the bus on the rising edge of PCS. > 0.9 V DCEN button Fig. 2-2: DC/DC startup DC/DC On Controller DSP operation =1 WSEN > 2 V
2.6.1. Parallel Input Output Interface (PIO) The parallel interface of the MAS 3504D consists of the lines PI0...PI4, PI8, PI12...PI19, and several control lines.
t0 RTW
t1
t2
t3
PIxx t4 PCS t5
Fig. 2-3: Parallel Data Output (PIO) Timing
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Table 2-1: PIO Output Mode Timing1) Symbol t0 t1 t2 t3 t4 t5
1)
2.6.3. Parallel Data Input Max. 1800 Unit In decoding mode, PIO lines PI12...PI19 are switched to the MAS 3504D data input which hence will be an 8bit parallel input port with MSB first (at position PI19) for the G.729 bit stream data. In order to write data to this parallel port, a special handshake protocol has to be used by the controller (see Fig. 2-4).
Pin Name RTW, PCS PCS PCS, RTW RTW PI PI
Min. 0.010 0.330 0.010 0.330 0.330 0.081
s s s
10000
s s s
2.6.3.1. DMA Handshake Protocol The data transfer can be started after the EOD pin of the MAS 3504D is set to high. After verifying this, the controller indicates the transmission of data by activating the PR line. The MAS 3504D responds by setting the RTR line to the low level. The MAS 3504D reads the data PI[19:12] after the rising edge of the PR. The next data word write operation will again be initialized by setting the PR line via the controller. Please refer to Figure 2-4 and Table 2-2 for the exact timing.
see Figure 2-3
tst tr tpd
trtrq
trpr
teod
teodq
high EOD low high PR tpr low high RTR tset th low high low Byte 1 Byte 15 MAS 3504D latches the PIO DATA
PI[19:12]
Fig. 2-4: Handshake protocol for writing G.729 data to the PIO-DMA
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MAS 3504D
2.6.3.2. End of DMA Transfer The above procedure will be repeated until the MAS 3504D sets the EOD signal to "0", which indicates that the transfer of one data block has been executed. Subsequently, the controller should set PR to "0", wait until EOD rises again, and then repeat the procedure ((see Section 2.6.3.1. on page 9)) to send the next block of data. The DMA buffer is 10 bytes long (one frame). The recommended PIO DMA conditions and the characteristics of the PIO timing are given in Table 2-2. 2.6.4. Audio Input Interface (SDI) The A/D interface is a standard I2S interface (16/32 bit, stereo). This input is used for G.729 recording mode and must be slaved to the D/A output clock and wordstrobe signals. The interface is configurable by software to work in different modes. It is possible to choose: - inverted or non inverted word strobe (SOI), - no delay or delay of data related to word strobe - inverted or non inverted I2S-Clock (SOC). For further details see Section 3.5.4. on page 18 Table 2-2: PIO DMA Timing Symbol tst tr tpd tset th trtrq tpr trpr teod teodq PIO Pin PR, EOD PR, RTR PR, PI[19:12] PI[19:12] PI[19:12] RTR PR PR, RTR PR, EOD EOD Min. 0.010 40 120 160 160 200 480 40 40 2.5 Max. 2000 160 480 no limit no limit 30000 no limit no limit 160 500 Unit 2.6.5. Audio Output Interface (SDO) The audio output interface of the MAS 3504D is a standard I2S interface. As the G.729 standard is only working on mono signals, the same signal is written to both output channels (left and right). The interface is configurable by software to work in different modes. It is possible to choose: - 16 or 32 bit/sample modes, - inverted or non inverted word strobe (SOI), - no delay or delay of data related to word strobe - inverted or non inverted I2S-clock (SOC). For further details see Section 3.5.4. on page 18
s
ns ns ns ns ns ns ns ns
s
10
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MAS 3504D
2.6.5.1. Example 1:16 Bits/Sample (I2S Compatible Data Format) A schematic timing diagram of the SDO interface in 16 bit/sample mode with delayed data by 1 clock cycle is shown in Fig. 2-5.
Vh SOC Vl Vh SOD V l Vh Vl left 16-bit audio sample right 16-bit audio sample
15 14 13 12 11 10 9 8 7 654 3 2 1 0 15 14 13 12 11 10 9 8 76543210
SOI
Fig. 2-5: Schematic timing of the SDO interface in 16bit/sample mode
2.6.5.2. Example 2:32 Bit/Sample (Inverted SOI) If the serial output generates 32 bits per audio sample, only the first 20 bits will carry valid audio data. The 12 trailing bits are set to zero by default (see Fig. 2-6).
SOC
Vh Vl
...
...
SOD
Vh Vl Vh
31 30 29 28 27 26 25
... 7
6 5 4 3 2 1 0 31 30 29 28 27 26 25
... 7
6543210
SOI
Vl
left 32-bit audio sample
right 32-bit audio sample
Fig. 2-6: Schematic timing of the SDO interface in 32 bit/sample mode
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MAS 3504D
3. Control Interfaces 3.1. I2C Bus Interface The MAS 3504D is controlled via the I2C bus slave interface. Due to the internal architecture of the MAS 3504D, the IC cannot react immediately to an I2C request. The typical response time is about 0.5 ms. If the MAS 3504D cannot accept another complete byte of data, it will hold the clock line I2C_CL LOW to force the transmitter into a wait state. The positions within a transmission where this may happen are indicated by 'Wait' in Section 3.3. on page 14. The maximum wait period of the MAS 3504D during normal operation mode is less than 4 ms. Table 3-1: I2C Bus Device Addresses MAS 3504D device address MAS_I2C_ADR Write 3Ahex Read 3Bhex
3.1.1. Device Address and Subaddresses The IC is selected by transmitting the MAS 3504D device addresses. (see Table 3-1). Writing is done by sending the device write address, (3Ahex) followed by the subaddress byte (68hex) and two or more bytes of data. Reading is done by sending the write device address (3Ahex), followed by the subaddress byte (69hex). Without sending a stop condition, reading of the addressed data is completed by sending the device read address (3Bhex) and reading n-bytes of data. By means of the RESET bit in the CONTROL register, the MAS 3504D can be reset by the controller.
Table 3-2: Control Register (Subaddress: 6Ahex) Name CONTROL Subaddress 6Ahex Bit [8] 1 : Reset 0 : normal Bit : 0-7, 9-15 0
Table 3-3: I2C Bus Subaddresses Name CONTROL_MAS WR_MAS RD_MAS Binary Value 0110 1010 0110 1000 0110 1001 Hex Value 6Ahex 68hex 69hex Mode Write Write Write Function control subaddress (see Table 3-2) write subaddress read subaddress
I2C_DA S I2C_CL
1 0 P
Fig. 3-1: I2C bus protocol (MSB first; data must be stable while clock is high) I2C-Bus Start Condition from master I2C-Bus Stop Condition from master Acknowledge-Bit: LOW on I2C_DA from slave or master Not Acknowledge-Bit: HIGH on I2C_DA from master to indicate `End of Read' I2C-Clock line is held low, while the MAS 3504D is processing the I2C command. This waiting time is max. 1 ms
Note: S = P= A= N= Wait =
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3.2. Command Structure The I2C control of the MAS 3504D is done completely via the I2C data register by using a special command syntax. The commands are executed by the MAS 3504D during its normal operation without any loss or interruption of the incoming data or outgoing audio data stream. These I2C commands allow the controller to access internal states, RAM contents, internal hardware control registers, and to download software modules. The command structure allows sophisticated control of the MAS 3504D. The registers of the MAS 3504D are either general purpose, e.g. for program flow control, or specialized registers that directly affect hardware blocks. The unrestricted access to these registers allows the system controller to overrule the firmware configuration. The MAS 3504D firmware scans the I2C interface periodically and checks for pending or new commands. Table 3-4 on page 13 shows the basic controller commands that are available by the MAS 3504D. 3.2.1. Conventions for the Command Description The description of the various controller commands uses the following formalism: - A data value is split into 4-bit nibbles which are numbered beginning with 0 for the least significant nibble. - Data values in nibbles are always shown in hexadecimal notation indicated by a preceding $. - A hexadecimal 20-bit number d is written, e.g. as d = $17C63, its five nibbles are d0 = $3, d1 = $6, d2 = $C, d3 = $7, and d4 = $1. - Abbreviations used in the following descriptions: a address d data value n count value o offset value r register number x don't care - Variables used in the following descriptions: dev_write $3A dev_read $3B data_write $68 data_read $69
Table 3-4: Basic Controller Commands Code [hex] 0 1 9 A B D E F Command run write register write to memory read register read memory Comment Start execution of an internal program. (Run 0 means freeze operating system.) An internal register of the MAS 3504D can be written directly to by the controller. A block of the DSP memory can be written to by the controller. This feature may be used to download alternate programs. The controller can read an internal register of the MAS 3504D. A block of the DSP memory can be read by the controller.
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MAS 3504D
3.3. Detailed MAS 3504D Command Syntax 3.3.1. Run
S S DW W A data_write A a3,a2 A a1,a0 W A P DW W A data_write A A A A A A,0 n3,n2 a3,a2 d3,d2 $0,$0 A A A A A $0,$0 n1,n0 a1,a0 d1,d0 $0,d4 W W W W W
3.3.3. Write D0 Memory
The `run' command causes the start of a program part at address a = (a3, a2, a1, a0). The nibble a3 is restricted to 0hex or 1hex which also acts as command selector. Run with address a = 0hex will suspend the encoding/decoding function and only I2C commands are evaluated. This freezing is required if alternative software is downloaded into the internal RAM of the MAS 3504D. Detailed information about downloading is provided in combination with a MAS 3504D software development package or together with MAS 3504D software modules available from Micronas. Example: `run' at address 1hex (start of G.729 decoder) has the following I2C protocol:
<$3A><$68><$00><$01>
....repeat for n data values....
A A d3,d2 $0,$0 A A d1,d0 $0,d4 W W A P
n3..n0: number of words to be transmitted a3..a0: start address in MASD memory d4..d0: data value
The MAS 3504D has 2 memory areas of 2048 words each called D0 and D1 memory. For both memory areas, read and write commands are provided. Example: writing one word to address d0:0321hex has the following I2C protocol:
<$3A><$68><$A0><$00> (write D0 memory) <$00><$01> (1 word to write) <$03><$21> (start address) <$23><$45> (value = 12345hex) <$00><$01>
3.3.2. Write Register
S
DW
W
A data_write A
9,r1 d4,d3
A A
r0,d4 d2,d1
W W
A A P
3.3.4. Write D1 Memory The controller writes the 20-bit value (d = d4, d3, d2, d1, d0) into the MAS 3504D register (r = r1,r0). In contrast to memory cells, registers are always addressed individually, and they may also interact with built-in hardware blocks. A list of registers is given in Section 3.5. on page 16 Example: G.729 decoding is started by writing the value 1 into the register with the number FDhex:
<$3A><$68><$9F><$D1><$00><$00>
S
DW
W
A data_write A A A A A
B,0 n3,n2 a3,a2 d3,d2 $0,$0
A A A A A
$0,$0 n1,n0 a1,a0 d1,d0 $0,d4
W W W W W
....repeat for n data values....
A A d3,d2 $0,$0 A A d1,d0 $0,d4 W W A P
n3..n0: number of words to be transmitted a3..a0: start address in MASD memory d4..d0: data value
For further details, see `write D0 memory' command.
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3.3.5. Read Register 3.3.7. Read D1 Memory
1) send command
S DW W A data_write A D,r1 A r0,$0 W A P
1) send command
S DW W A data_write A A S W DR x,x W A A x,d4 W N P A F,$0 n3,n2 a3,a2 A A A $0,$0 n1,n0 a1,a0 W W W A P
2) get register value
S DW A W A data_read A A d1,d0 A
d3,d2
2) get memory value
S DW A W A data_read A A d1,d0 W S A DR $0,$0 W A $0,d4 W
r1, r0: register r d3..d0: data value in r x: don't care
d3,d2
....repeat for n data values....
The MAS 3504D has an address space of 256 registers. Some of the registers (r = r1, r0 in the figure above) are direct control inputs for various hardware blocks, others do control the internal program flow. In the next section, those registers that are of any interest with respect to the G.729 codec are described in detail. Example: Read the content of the PIO data register (C8hex):
<$3A><$68><$DC><$80> <$3A><$69><$3B> now read:
A
d3,d2
A
d1,d0
W
A
$0,$0
A
$0,d4
W
N
P
n3..n0: number of words a3..a0: start address in MASD memory d4..d0: data value
The `read D1 memory' command is provided to get information from memory cells of the MAS 3504D. It gives the controller access to all memory cells of the internal D1 memory.
3.3.6. Read D0 Memory
1) send command
S DW W A data_write A A A E,$0 n3,n2 a3,a2 A A A 0$,$0 n1,n0 a1,a0 W W W A P
2) get memory value
S DW A W A data_read A A d1,d0 W S A DR $0,$0 W A $0,d4 W
d3,d2
....repeat for n data values....
A d3,d2 A d1,d0 W A $0,$0 A $0,d4 W N P
n3..n0: number of words a3..a0: start address in MASD memory d4..d0: data value
The `read D0 memory' command is provided to get information from memory cells of the MAS 3504D. It gives the controller access to all memory cells of the internal D0 memory. Direct access to memory cells is an advanced feature of the DSP. It is intended for users of the MASC software development kit.
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MAS 3504D
3.4. Version Number Table 3-5 shows where the chip identification and the name of the software is located. 3.5.1. DC/DC Converter (Reg. 8Ehex) Table 3-5: MAS 3504D Version Addr. [hex] D1:FF6 Content name of MAS 3504D version description: "G.729a CODEC" Example Value 0x03504 3504 The DCCF Register controls both, the internal voltage monitor and the DC/DC converter. Between output voltage of the DC/DC converter and the internal voltage monitor threshold an offset exists which is shown in Table 3-8 on page 19. Please pay attention to the fact, that I2C protocol is working only if the processor works (WSEN = 1).However, the setting for the DCCF register will remain active if the DCEN and WSEN lines are deasserted. The DC/DC converter may generate interference noise that could be unacceptable for some applications. Thus the oscillator frequency may be adjusted in 32 steps in order to allow the system controller to select a base frequency that does not interfere with an other application. The CLKI input provides the base clock fCLKI for the frequency divider whose output is made symmetrical with an additional divider by two. The divider quotient is determined by the content of the DCCF register. This register allows 32 settings generating a DC/DC converter clock frequency fdc between: f CLKI f SW = -----------------------2 (m + n) system crash of the decoder operation which can only be restored by a reset.
D1:FF9 D1:FFA D1:FFB D1:FFC D1:FFD D1:FFE D1:FFF
0x0472e 0x03732 0x03961 0x02043 0x04f44 0x04543 0x02020
G. 72 9A C OD EC
3.5. Register Table In Table 3-6, the internal registers for controlling the MAS 3504D are listed. They are accessible by `register read/write' I2C commands (see Section 3.3. on page 14). For a more detailed register usage (see Table 3-8 on page 19). Important note! Writing into undocumented registers or read-only registers is always possible, but it is highly recommended not to do so. It may damage the function of the firmware and may even lead to a complete
n {0, 15} , m {32, 16}
(EQ 1)
3.5.2. User Control (Reg. FDhex) The UserControl register is used to switch between basic operation modes. On startup, after a software reset or a "run 1" command it is set to 0hex. The MAS 3504D sets the control registers to default values, switches off all interfaces (except I2C) and waits for a change in UserControl.
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Table 3-6: Command Register Table Address (hex) 8E FD FC 74 E1 61 FA Mode w r/w r/w r/w r/w r/w r/w Function DC/DC operation control Operation mode selection Output volume Serial interface wordlength Configuration of the I2S audio input interface Configuration of the I2S audio output interface Special operation options Default (hex) 8000 0 7FFFF 0 4 4000 0 Name DCCF UserControl Volume Wordlength InputConfig OutputConfig HWControl
3.5.2.1. Data Transmission Format The codec is working on a page basis. That means, that encoding and decoding is performed in blocks of 50 G.729 frames, whereas each frame consists of 10 bytes in byte swapped order (see Fig. 3-2). Therefore most changes to the UserControl register become effective when processing of a page is finished. The pages are optionally preceeded by 10 byte header frames (see Table 3-7). Table 3-7: Content of Page Header
To switch to encoder operation mode, UserControl has to be set to 3hex. Then 50 frames are encoded and sent via the PIO interface. This is repeated until the UserControl register is changed. If the transmission of headers is enabled, each page of 50 frames is preceeded by a header frame as shown in Table 3-7. To switch off the encoder, UserControl has to be set to 0hex. Then the encoding and sending of frames continues until the end of the current page and the operation mode is set to stop.
3.5.2.3. Decoder Operation Byte 1 2 3 4 5 6 7 8 9 10 The routines for the G.729 decoder mode are completely located in the MAS 3504D firmware. So there is no need to download the encoder routine in a decode only application. To switch to decoder operation mode, UserControl has to be set to 1hex. For decoding with slow speed, set UserControl to 11hex. For decoding with fast speed, set UserControl to 21hex. Then the decoder is requesting several frames via the PIO interface to fill its internal buffer. If enough data is available, 50 frames are decoded. This is repeated until the UserControl register is changed. If the transmission of headers is enabled, a header frame (as shown in Table 3-7) has to be sent before each page of 50 frames. To switch off the decoder, UserControl has to be set to 0hex. Then the decoding of frames continues until the end of the current page and the operation mode is set to stop.
Value 64 6D 72 31 64 61 74 61 F4 01 [hex]
Switching from encoding to decoding mode or vice versa directly is not allowed. Instead the controller has to send a stop request to the MAS 3504D (writing 0hex to UserControl). Then the controller has to keep on sending data in decoding mode or receive data in encoding mode until the current page of 50 frames is finished. After this run out time, the encoding or decoding can be started again.
3.5.2.2. Encoder Operation To enable the G.729 encoder mode, a special routine has to be downloaded to the MAS 3504D IC first. This has to be done with an I2C download before the encoder is started the first time. If the encoder is started without downloading the routine, the behavior of the IC is unpredictable.
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3.5.2.4. Pause and Mute If the pause bit is set, the processing continues until the current page is finished and then en-/decoding is paused. The pause mode lasts until the pause bit is cleared again or the mode is set to 0. If the mute bit is set, the output is muted immediately. Note that the other bits of the UserControl register have to stay on their old values when switching to pause mode. 3.5.4.2. Input Configuration (Reg. 61hex) The content of this register is set on startup by the firmware. Additional to the Wordlength setting for the serial interfaces, some other settings can be made.
3.5.4.3. Output Configuration (Reg. E1hex) The content of this register is set on startup by the firmware. Additional to the Wordlength setting for the serial interfaces, some other settings can be made.
3.5.3. Volume Control (Reg. FChex) Volume control is implemented in the MAS 3504D. It allows to adjust the output volume linear from 0hex (silence) to 7FFFFhex (original volume). 3.5.4. Interface Control All the interface control registers have to be written before the encoder or decoder is started by writing to the UserControl register. Otherwise they have no effect until the operation mode is changed.
3.5.5. Hardware Control (Reg. FAhex) The HWControl register is used to set special operation options. If the page headers bit is 0, a header frame is transferred in front of each page of 50 data frames. If the header bit is 1, all the frames are G.729 data frames. Bits 2 and 1 are used to select input channels for encoding. If both bits are set to 0, the left and right channel are added to get the mono input signal. If only one of this bits is 1, only the corresponding channel is used as input.
3.5.4.1. Wordlength Control (Reg. 74hex) A value of 0hex sets wordlength on SDI and SDO interfaces to 32 bit. 1hex sets wordlength to 16 bit.
page frame frame frame header 1 2 3
...
frame frame page frame frame 49 49 header 51 52 ... 10ms 10ms ...
...
frame frame page frame frame 99 100 header 101 102
...
$64 $6d $72 $31 $64 $61 $74 $61 $f4 $01
byte byte byte byte byte byte byte byte byte byte 2 1 4 3 6 7 10 9 5 8
Fig. 3-2: Schematic timing of the data transmission with preceeding header
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Table 3-8: Detailed Register Usage Address (hex) 61 Mode r/w Function Configuration of the I2S audio input interface bit[19:12] bit[11] not used, set to 0 additional delay of data related to word strobe 0 no delay 1 1 bit delay not used, set to 0 input word strobe signal 0 standard timing 1 inverted timing not used, set to 0 input clock signal 0 standard timing 1 inverted timing not used, set to 0 0 Wordlength Default (hex) 4 Name InputConfig
bit[10:6] bit[5]
bit[4:3] bit[2]
bit[1:0] 74 r/w
Serial output interface wordlength bit[19:1] bit[0] not used, set to 0 wordlength 0 32 bit/sample 1 16 bit/sample
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Table 3-8: Detailed Register Usage, continued Address (hex) 8E Mode w Function DC/DC operation control bit[19:17] not used, set to 0 Default (hex) 8000 Name DCCF
bit[16:14,9] output voltage / internal voltage monitor (PUP signal becomes inactive when output is below the monitoring voltage) Setting bit [16:14] and [9] 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DC/DC-Converter Output Voltage [V] 3.57 3.46 3.35 3.25 3.14 3.04 2.94 2.83 2.73 2.63 2.52 2.42 2.32 2.22 2.12 2.02 Internal Monitor Voltage [V] 3.38 3.27 3.16 3.06 2.95 2.85 2.75 2.64 2.54 2.44 2.33 2.23 2.13 2.03 1.93 1.82
bit[13:10,8] DC/DC-converter switching frequency fSW [kHz] Setting bit [13:10] 11 11 11 11 10 10 10 10 01 01 01 01 00 00 00 00 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 Frequency/kHz bit [8] = 0 156 160 163 167 171 175 179 184 188 194 199 204 210 216 223 230 not used, set to 0 Frequency/kHz bit [8] = 1 128 245 253 263 272 283 295 307 320 335 351 368 387 409 433 460
bit[7:0]
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Table 3-8: Detailed Register Usage, continued Address (hex) E1 Mode r/w Function Configuration of the I2S audio output interface bit[19:15] bit[14] not used, set to 0 output clock signal 0 standard timing 1 inverted timing not used, set to 0 additional delay of data related to word strobe 0 no delay 1 1 bit delay not used, set to 0 output word strobe signal 0 standard timing 1 inverted timing not used, set to 0 0 HWControl Default (hex) 4000 Name OutputConfig
bit[13:12] bit[11]
bit[10:6] bit[5]
bit[4:0] FA r/w
Special operation options bit[19:3] bit[2:1] not used, set to 0 input channel matrixing 00 add left/right channel 01 input only from right channel 10 input only from left channel 11 not allowed page headers 0 enable 1 disable
bit[0]
FC
r/w
Output volume bit[19:0] linear volume level
7FFFF
Volume
FD
r/w
Operation mode selection bit[19:6] bit[5:4] not used, set to 0 decoding speed 00 8 kHz (normal) 01 6 kHz (slow) 10 12 kHz (fast) 11 not allowed mute audio output 0 disable 1 enable pause encoder/decoder 0 disable 1 enable mode 00 01 10 11 idle decode not allowed encode
0
UserControl
bit[3]
bit[2]
bit[1:0]
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MAS 3504D
4. Specifications 4.1. Outline Dimensions
10 x 0.8 = 8 0.1 0.17 0.06 33 34 13.2 0.2 23 22 10 0.1 0.8 10 0.1 0.46 0.8
44 1 11 13.2 0.2
12
2.0 0.1 2.15 0.2 0.1
0.34 0.05
SPGS706000-5(P44)/1E
Fig. 4-1: Plastic Metric Quad Flat Pack 44-Pin (PMQFP44) Weight approximately 0.4 g Dimensions in mm
A1 Ball Pad Corner 7 6 5 4 3 21
1.4 0.36
Laser marked pin 1
A B 6 x 0.8 = 4.8 C 0.8 D E F G
7
0.8 6 x 0.8 = 4.8 7
SPGS708000-1(P49)/1E
Fig. 4-2: Low-Profile Fine-Pitch Ball Grid Array 49-Pin (LFBGA49) Weight approximately 0.13 g Dimensions in mm
22
10 x 0.8 = 8 0.1
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4.2. Pin Connections and Short Descriptions NC LV X not connected, leave vacant If not used, leave vacant obligatory, pin must be connected as described in application information VDD connect to positive supply VSS connect to ground Pin No.
PMQFP 44-pin LFBGA 49-ball
Pin Name
Test Alias in ()
Type
Connection
(If not used)
Short Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
C3 C2 B1 D2 C1 D1 E2 E1 F2 F1 G1 E3 F3 G2 F4 G3 E4 G4 F5 G5 F6 G6 E5 E6 F7 D6
TE POR I2CC I2CD VDD VSS DCEN EOD RTR RTW DCSG DCSO VSENS PR PCS PI19 PI18 PI17 PI16 PI15 PI14 PI13 PI12 SOD SOI SOC (PI11) (PI10) (PI9)
IN IN IN/OUT IN/OUT SUPPLY SUPPLY IN OUT OUT OUT SUPPLY OUT IN IN IN IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT OUT OUT OUT
VSS X X X X X VSS LV LV LV VSS VSS VDD X X LV LV LV LV LV LV LV LV LV LV LV
Test Enable Reset, Active Low I2C Clock Line I2C Data Line Positive Supply for Digital Parts Ground Supply for Digital Parts Enable DC/DC Converter PIO End of DMA, Active Low PIO Ready to Read, Active Low PIO Ready to Write, Active Low DC Converter Transistor Ground DC Converter Transistor Open Drain DC Converter Voltage Sense PIO-DMA Request or Read/Write PIO Chip Select, Active Low PIO Data [19] PIO Data [18] PIO Data [17] PIO Data [16] PIO Data [15] PIO Data [14] PIO Data [13] PIO Data [12] data bit [7], MSB data bit [6] data bit [5] data bit [4] data bit [3] data bit [2] data bit [1] data bit [0]
Serial Output Data Serial Output Frame Identification Serial Output Clock
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Pin No.
PMQFP 44-pin LFBGA 49-ball
Pin Name
Test Alias in ()
Type
Connection
(If not used)
Short Description
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
E7 D7 C6 C7 B6 B7 A7 B5 A6 B4 A5 C4 A4 B3 A3
PI8 XVDD XVSS SID SII SIC PI4 PI3 PI2 PI1 PI0 CLKO PUP WSEN WRDY (PI7) (PI6) (PI5)
IN SUPPLY SUPPLY IN IN IN IN IN IN IN IN OUT OUT IN OUT
LV X X VSS VSS VSS LV LV LV LV LV LV LV X LV
Not used Positive Supply of Output Buffers Ground of Output Buffers Serial Input Data Serial Input Frame Identification Serial Input Clock Not used Not used Not used Not used Not used Not used Power Up (status of voltage supervision) Enable DSP and Start DC/DC Converter If WSEN = 0: valid clock input at CLKI If WSEN = 1: clock synthesizer PLL locked Supply for Analog Circuits Clock Input Ground Supply for Analog Circuits
42 43 44
B2 A2 A1
AVDD CLKI AVSS
SUPPLY IN SUPPLY
VDD X VSS
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4.2.1. Pin Descriptions 4.2.1.1. Power Supply Pins Connection of all power supply pins is mandatory for the function of the MAS 3504D. VDD VSS SUPPLY SUPPLY 4.2.1.4. Parallel Interface Lines The VDD/VSS pair is internally connected with all digital modules of the MAS 3504D. XVDD XVSS SUPPLY SUPPLY 4.2.1.4.1. PIO Handshake Lines 'PIO handshake lines' are used in operation mode. PIO-DMA mode is used in input mode and P mode in output mode. PCS IN 4.2.1.3. Control Lines I2CC I2CD SCL SDA IN/OUT IN/OUT
Standard I2C control lines. Normally there are Pull-upresistors tied from each line to VDD.
The XVDD/XVSS pins are internally connected with the pin output buffers. AVDD AVSS SUPPLY SUPPLY
The AVDD/AVSS pair is connected internally with the analog blocks of the MAS 3504D, i.e. clock synthesizer and supply voltage supervision circuits.
The 'PIO chip select' is driven from microcontroller to activate data output from MAS 3504D to the bus. Data is output to the bus on the falling edge of PCS and is removed on the rising edge of PCS. PR IN
4.2.1.2. DC/DC Converter Pins DCEN IN
The 'PIO request' must be set to `1' to validate data output from MAS 3504D. RTR OUT
The DCEN input signal enables the DC/DC converter operation. DCSG SUPPLY
`Ready to read' is driven from the MAS 3504D in PIO/ DMA input mode. RTW OUT
The `DC converter Signal Ground' pin is used as a basepoint for the internal switching transistor of the DC/DC converter. It must always be connected to ground. DCSO OUT
`Ready to write' is driven from MAS 3504D to indicate that data is available in PIO output mode. EOD OUT
`End of DMA' is supported by the built-in firmware in PIO-DMA input mode.
DCSO is an open drain output and should be connected with external circuitry (inductor/diode) to start the DC/DC converter. When the DC/DC converter is not used, it has to be connected to VSS. VSENS IN
4.2.1.4.2. PIO Data Lines PI19...PI12 PARALLEL DATA OUT/IN
The VSENS pin is the input for the DC/DC converter feedback loop. It must be connected directly with the Schottky diode and the capacitor as shown in Fig. 2-1 on page 7. When the DC/DC converter is not used, it has to be connected to VDD.
These pins are used to send or receive compressed data.
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4.2.1.5. Voltage Supervision And Other Functions CLKI IN 4.2.1.8. Miscellaneous POR IN
This is the clock input of the MAS 3504D. CLKI should be a buffered output of a crystal oscillator. Standard clock frequency is 18.432 MHz. CLKO This pin has no function. PUP OUT OUT
The Power On Reset pin is used to reset the digital parts of the MAS 3504D. POR is a low active signal. TE IN
The TE pin is for production test only and must be connected with VSS in all applications.
4.2.2. Pin Configurations The PUP output indicates that the power supply voltage exceeds its minimal level (software adjustable).
XVDD
WSEN
IN
SII SIC PI4
XVSS SID
PI8 SOC SOI SOD PI12
WSEN enables DSP operation and switches on the DC/DC-converter. WRDY OUT
33 32 31 30 29 28 27 26 25 24 23
WRDY has two functions depending on the state of the WSEN signal. If WSEN = '0', it indicates that a valid clock has been recognized at the CLKI clock input. If WSEN = '1', the WRDY output will be set to `0' until the internal clock synthesizer has locked to the incoming audio data stream, and thus, the CLKO clock output signal is valid.
PI3 PI2 PI1 PI0 CLKO PUP WSEN WRDY AVDD CLKI AVSS
34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11
22 21 20 19 18
PI13 PI14 PI15 PI16 PI17 PI18 PI19 PCS PR VSENS DCSO
MAS 3504D
17 16 15 14 13 12
4.2.1.6. Serial Input Interface SID SII SIC IN IN IN
TE POR I2CC I2CD VDD VSS
DCSG RTW RTR EOD DCEN
Data, Frame Indication, and Clock line of the serial input interface. The SII indicates whether the left or the right audio sample is transmitted.
Fig. 4-3: PMQFP44 package
4.2.1.7. Serial Output Interface SOD SOI SOC OUT OUT OUT
Data, Frame Indication, and Clock line of the serial output interface. The SOI indicates whether the left or the right audio sample is transmitted.
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4.2.3. Internal Pin Circuits
TTLIN
DCSO
DCSG Fig. 4-4: Input pins PCS, PR VSS Fig. 4-10: Input/Output pins DCSO, DCSG
VDD Fig. 4-5: Input pin TE, DCEN P
N VSS Fig. 4-11: Output pins WRDY, RTW, EOD, RTR, CLKO, PUP
Fig. 4-6: Input pins WSEN, POR
VSENS
Fig. 4-7: Input pin CLKI
VDD P
VSS Fig. 4-12: Input pin VSENS
N VSS Fig. 4-8: Input/Output pins PI0...PI4, PI8, SOC, SOI, SOD, PI12...PI19
VDD P
N VSS
VDD Fig. 4-13: Input/Output pins SIC, SII, SID
N VSS Fig. 4-9: Input/Output pins I2CC, I2CD
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4.2.4. Electrical Characteristics 4.2.4.1. Absolute Maximum Ratings Symbol TA Parameter Ambient operating temperature - operating conditions - extended temperature range1) TC Case operating temperature - LFBGA49 - PMQFP44 TS PMAX Storage temperature Power dissipation for all packages Supply voltage VDD, XVDD, AVDD VDD, XVDD, AVDD 0 0 95 95 125 400 C mW 0 -30 85 85 C Pin Name Min. Max. Unit C
-40
VSUP
5.5
V
VIdig IIdig VII2C IOut IOutDC
1)
Input voltage, all digital inputs Input current, all digital inputs Input Voltage, I2C-Pins Current, all digital outputs Current DCSO I2CC I2CD
-0.3 -20 -0.3
VSUP +0.3 +20 5.5 0.5 1.5
V mA V A A
The functionality of the device in the "extended temperature range" was checked by electrical characterization on sample base. Data sheet parameters are valid for "operating conditions" only.
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
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4.2.4.2. Recommended Operating Conditions Symbol TA Parameter Ambient operating temperature - operating conditions - extended temperature range1) VSUP Supply voltage for G.729 decoder operation and download software Supply voltage for G.729 encoder operation Reference Frequency Generation CLKF CLKI_V CLKAmp Levels IIL27 IIH36 IIH33 IIH30 IILD IIHD Trf Input Low Voltage @VSUP = 2.5 V ... 3.6 V Input High Voltage @VSUP = 2.5 V ... 3.6 V Input High Voltage @VSUP = 2.5 V ... 3.3 V Input High Voltage @VSUP = 2.5 V ... 3.0 V Input Low Voltage Input High Voltage PI2), SII, SIC, SID, PR, PCS, TE, PI, SII, SIC, SID, PR, PCS, CLKI SIC, CLKI 40 50 POR I2CC, I2CD, DCEN, WSEN 0.4 1.8 1.7 1.6 0.4 VSUP- 0.5 10 V V V V V V Clock Frequency Clock Input Voltage Clock Amplitude CLKI 0 0.5 18.432 VSUP MHz V Vpp VDD, XVDD, AVDD 0 -30 2.5 3.0 3.0 3.3 85 85 3.6 3.6 C C V V Pin Name Min. Typ. Max. Unit
Rise / Fall time of digital inputs
ns
Dcycle
1) 2)
Duty cycle of clock inputs
60
%
The functionality of the device in the "extended temperature range" was checked by electrical characterization on a sample base. Data sheet parameters are valid for "operating conditions" only. i = 0 to 4, 8 , 12 to 19
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Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
DC-DC converter external circuitry C1 VF L
3) 4) 5)
Blocking Capacitor (25 m ESR)3) Schottky Diode Forward voltage4) Inductance of Ferrite ring core coil5) (50 m),VAC 616/103
VSENS, DCSG DCSO, VSENS DCSO 0.35
330 0.45 20
F
V
H
Sanyo Oscon 6SA330M (distributed by Endrich Bauelemente, D-72202 Nagold-lselshausen, www.endrich.com) ZETEX ZMCS1000 (distributed by ZETEX, D-81673 Munchen, europe.sales@zetex.com), standard Schottky 1N5817 C8 R/4L, SDS0604 (distributed by Endrich Bauelemente, s.a.), VAC 616/103
4.2.4.3. Characteristics Typ. values at TA = 27 C, VSUP = 3.3 V, CLKF = 18.432 MHz, duty cycle = 50%
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
Supply Voltage ISUP Current Consumption VDD, XVDD, AVDD 46 25 15 Digital Outputs and Inputs VDOL VDOH Output Low Voltage Output High Voltage PI1), SOI, SOC, SOD, EOD, RTR, RTW, WRDY, PUP, CLKO PI, SII, SIC, SID, PR, PCS, CLKI 0.3 VSUP0.3 V V @ ILOAD = 6 mA @ ILOAD = 6 mA mA mA mA 3.3 V, G.729 encoding 3.3 V, G.729 decoding 3.3 V, waiting mode
CDIGL IDLeak
Input Capacitance Digital Input Leakage Current
7 -1 1
pF A 0 V < Vpin < VSUP
1)
i = 0 to 4, 8 , 12 to 19
30
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4.2.4.3.1. I2C Characteristics at TA = -30 to 85 C, VSUP = 2.5 to 3.6 V, typ. values at TA = 27 C, VSUP = 3.3 V, CLKF = 18.432 MHz, duty cycle = 50%
Symbol RON fI2C tI2C1 tI2C2 tI2C3 tI2C4 tI2C5 tI2C6 VI2COL II2COH tI2COL1 tI2COL2 TW Parameter Output Resistance I2C Bus Frequency I2C START Condition Setup Time I2C STOP Condition Setup Time I2C Clock Low Pulse Time I2C Clock High Pulse Time I2C Data Hold Time before Rising Edge of Clock I2C Data Hold Time after Falling Edge of Clock I2C Output Low Voltage I2C Output High Leakage Current I2C Data Output Hold Time after Falling Edge of Clock I2C Data Output Setup Time before Rising Edge of Clock Wait time Pin Name I2CC, I2CD I2CC I2CC, I2CD I2CC, I2CD I2CC I2CC I2CC I2CC I2CC, I2CD I2CC, I2CD I2CC, I2CD I2CC, I2CD I2CC, I2CD 20 250 0 0.5 4 300 300 1250 1250 80 80 0.3 1 Min. Typ. Max. 60 400 Unit kHz ns ns ns ns ns ns V uA ns ns ms fI2C = 400 kHz ILOAD = 5 mA VI2CH = 3.6 V Test Conditions ILOAD = 5 mA, VSUP = 2.7 V
1/fI2C
tI2C4
H L I2CC tI2C1 H L I2CD as input tI2COL2 H L I2CD as output tI2C5
tI2C3
tI2C6
tI2C2
tIC2OL1
Fig. 4-14: I2C timing diagram
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4.2.4.3.2. I2S Bus Characteristics - SDI at TA = -30 to 85 C, VSUP = 3.0 to 3.6 V, typ. values at TA = 27 C, VSUP = 3.3 V, CLKF = 18.432 MHz, duty cycle = 50%
Symbol tSICLK tSIIDS Parameter I2S Clock Input Period I2S Data SetupTime before Falling Edge of Clock I2S Data Hold Time Burst Wait Time Pin Name SIC SIC, SID SID SIC, SID Min. 960 50 tSICLK100 Typ. Max. Unit ns ns Test Conditions
tSIIDH tbw
50 480
ns
TSICLK H SIC L H SII L
H SID L TSIIDS Fig. 4-15: Serial input TSIIDH
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4.2.4.3.3. I2S Characteristics - SDO at TA = -30 to 85 C, VSUP = 3.0 to 3.6 V, typ. values at TA = 27 C, VSUP = 3.3 V, CLKF = 18.432 MHz, duty cycle = 50%
Symbol tSOCLK tSOISS tSOODC Parameter I2S Clock Output Period I2S Wordstrobe Hold Time after Falling Edge of Clock I2S Data Hold Time after Falling Edge of Clock Pin Name SOC SOC, SOI SOC, SOD 10 10 Min. Typ. 1953 tSOCLK/ 2 tSOCLK/ 2 Max. Unit ns ns ns Test Conditions 8 kHz stereo 32 bit/sample
TSOCLK SOC
H L H L
TSOISS TSOISS
SOI
SOD
H L
TSOODC
Fig. 4-16: Serial output SOI
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4.2.4.4. DC/DC Converter Characteristics at TA = -30 to 85 C, VSUP = 3.0 V, CLKF = 14.725 MHz, fsw = 230 kHz, typ. values at TA = +27 C Unless otherwise noted: VOUT = 3.0 V, VIN = 1.2 V Note: The following characterizations were made with voltage and clock input that is not usable for G.729 applications.
Symbol VIN1 Parameter Minimum start-up input voltage Pin Name
1)
Min.
Typ. 0.9
Max. 1.1
Unit V
Test Conditions ILOAD = 0 mA DCCF = 08000hex (Reset) ILOAD = 55 mA, DCCF = 08000hex (Reset) ILOAD = 250 mA, DCCF = 08000hex (Reset)
VIN2
Minimum operating input voltage
1)
0.6
0.9
V
1.3
1.8
V
VOUT
Output voltage range Bits 16..14, Bit 9 of DCCF Register [hex]: 1C000 18000 14000 10000 0C000 08000 04000 00000 1C200 18200 14200 10200 0C200 08200 04200 00200
VSENS
3.567 3.460 3.354 3.248 3.144 3.039 2.935 2.831 2.729 2.625 2.524 2.422 2.321 2.219 2.118 2.017 VSENS -3.6 3.6
V
VIN = 1.2 V ILOAD = 50 mA
VOTOL
Output voltage tolerance
%
ILOAD = 50 mA Tj = 27 C VIN = 1.2 V VIN = 0.9..1.5 V VIN = 1.8..3.0 V ILOAD = 50mA ILOAD = 250 mA, VOUT = 3.5 V, VIN = 2.4 V ILOAD = 50...150 mA, ILOAD = 50..250 mA, VOUT = 3.5 V, VIN = 2.4 V
ILOAD1 ILOAD2 dVOUT/dVIN/ VOUT dVOUT/dVIN/ VOUT dVOUT/VOUT dVOUT/VOUT
Output current
VSENS
150 250
mA mA %/V %/V
Line regulation Line regulation
VSENS VSENS
0.35 0.7
Load regulation Load regulation
VSENS VSENS
-0.5 -0.5
% %
1)
All measurements are made with a C8 R/4L 20 H, 25 m ferrite ring-core coil, Zetex ZLMCS1000 Schottky diode, and Sanyo/Oscon 6SA330M 330 F, 25 m ESR capacitors at input and output (see Section 4.2.4. on page 28).
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Micronas
MAS 3504D
Symbol hmax ISUPPLY IL,MAX RON ILEAK
Parameter Maximum efficiency Supply current Inductor current limit Switch on-resistance Switch leakage current
Pin Name
Min.
Typ. 90
Max.
Unit %
Test Conditions VIN = 3.0 V, VOUT = 3.5 V VIN = 3.0 V, ILOAD = 0, includ. switch current
VSENS DCSO, DCSG DCSO, DCSG DCSO, DCSG DCSO, DCSG DCEN, PUP DCSO 156
1.1 1.0 0.4 0.1
5 1.4
mA A
1
A
Tj = 27 C, converter = off, ILOAD = 0 A Depending on DCCF VIN = 1.0 V, ILOAD = 1 mA, PUPLIM = 010 (Reset) VSENS < 1.9 V
fSW tSTART
Switch frequency Start up time asserting to PUP
230 8
460
kHz ms
fSTARTUP
VSENSE
250
kHz
Micronas
35
MAS 3504D
4.2.4.5. Typical Performance Characteristics
Efficiency vs. Load Current (Vout=3.5V) 100
3.0 V 1.8 V
Efficiency vs. Load Current (Vout=3.0V) 100
2.4 V
80
Vin
80
Vin
Efficiency (%)
Efficiency (%)
60
60
0.7 V
40 Vin: 3.0V 2.4V 1.8V 10 -4 10-3 10-2 10-1 1
40
20
20
Vin: 2.4V 1.8V 1.5V 1.2V 0.9V 0.7V 10 -4 10-3 10-2 10-1 1
0
0 Load Current (A)
Load Current (A)
Efficiency vs. Load Current (Vout=2.7V) 100
Vin 2.4 V
Efficiency vs. Load Current (Vout=2.2V) 100
Vin 1.5 V
80
1.2 V
80
Efficiency (%)
Efficiency (%)
60
60
0.7 V
40 Vin: 2.4V 1.8V 1.2V 0 10 -4 10-3 10-2 10-1 1 Load Current (A)
40 Vin: 1.5V 1.2V 0.9V 0.7V 10 -4 10-3 10-2 10-1 1
20
20
0 Load Current (A)
Fig. 4-17: Efficiency vs. Load Current
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Micronas
MAS 3504D
Output Voltage vs. Input Voltage Iload=250mA 3.6
3.5 V
Output Voltage vs. Input Voltage Iload=50mA 3.2
3.1 V
3.4
3
2.8 Output Voltage (V) Output Voltage (V) 3.2
3.1 V 2.7 V
2.6
3
2.4
2.2 V
2.8
2.7 V
2.2
2.6 1.5 2 2.5 3 3.5 Input Voltage (V)
Fig. 4-18: Output Voltage vs. Input Voltage
2 0.9 1.4 1.9 2.4 2.9 Input Voltage (V)
Output Voltage vs. Load Current 3.6
Vin
Output Voltage vs. Load Current 3.4
3.4
Vin=3V, 2.4V, 1.8V
3.2 3 Vin=1.5V, 0.9V
Vin
Output Voltage (V)
Output Voltage
3.2
2.8 2.6 2.4
Vin
3
2.8 2.2 2.6 0 Vin=2.4V 0.1 0.2 0.3 Vin=1.5V, 0.9V 2 0 0.02 0.04 0.06 0.08 Load Current (A)
Load Current (A)
Fig. 4-19: Output Voltage vs. Load Current
Micronas
37
MAS 3504D
0.8 Maximum Load Current (A)
Maximum Load Current vs. Input Voltage 6.0
No Load Supply Current vs. Input Voltage
0.6 2.2V 0.4
Vout
No Load Supply Current (mA)
3.5V
Vout = 3 V
4.0
0.2
Vout= 3.5V 3.1V 2.7V 2.2V
2.0
0 0 1 2 Input Voltage (V) 3
0 0 1 2 3 Input Voltage (V)
Fig. 4-20: Maximum Load Current vs. Input Voltage
Fig. 4-21: No Load Supply Current vs. Input Voltage
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Micronas
MAS 3504D
3V 3V
3V
3V 0A
0A 0A
500.00 s/Div Vin = 1.2 V; Vout = 3 V 1 Load Current 2 Output Voltage 3 Inductor Current 200.0 mA/Div 100.0 mV/Div / AC-coupled 500.0 mA/Div 1 2 3 4 V (DCEN) V (PUP) Inductor Current Output Voltage
500 s/Div Vin = 1 V; Iload = 0 mA 2.000 V/Div 2.000 V/Div 500.0 mA/Div 2.000 V/Div
Fig. 4-22: Load Transient-Response
Fig. 4-24: Startup Waveform
3V
2V
5.00 ms/Div Iload = 100 mA; Vout = 3 V 1 Vin 2.000 V/Div 2 Output Voltage 50.00 mV/Div / AC-coupled 3 Inductor Current 200.0 mA/Div Fig. 4-23: Line Transient-Response
Micronas
200 mA
39
MAS 3504D
5. Data Sheet History 1. Final data sheet: "MAS 3504D G.729 Annex A Voice Codec", Nov. 7, 2001, 6251-522-1DS. First release of the final data sheet.
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-522-1DS
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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Micronas

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